1. Field of Invention
Various embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a semiconductor memory device including a 3-dimensional (3D) structure.
2. Description of Related Art
As an industry in a field of a memory device, such as a nonvolatile memory device, has been highly developed, demands for high integration of the memory device have been increased. In the related art, integration of the memory device within a predetermined area is increased by a method of decreasing sizes of memory cells 2-dimensionally arranged on a semiconductor substrate. However, there is a physical limitation in decreasing the sizes of the memory cells. Accordingly, a method of highly integrating a memory device by 3-dimensionally arranging memory cells on a semiconductor substrate has been suggested. When the memory cells are 3-dimensionally arranged as described above, it is possible to efficiently utilize the area of the semiconductor substrate, and further improve a degree of integration compared to a case in which the memory cells are 2-dimensionally arranged. Particularly, when a 3D NAND flash memory device is implemented by 3-dimensionally arranging memory strings of the NAND flash memory device, which is advantageous to high integration, it is expected to maximize a degree of integration of the memory device, so that development of a 3D semiconductor memory device has been demanded.
FIG. 1 is a perspective view illustrating a structure of a 3D semiconductor memory device according to the related art. However, illustration of interlayer insulating layers is omitted for convenience of description.
As illustrated in FIG. 1A, a semiconductor device according to the related art includes U-shaped channel layers CH arranged in a first direction I-I′ and a second direction II-II′ crossing the first direction I-I′. Here, each of the U-shaped channel layers CH includes a pipe channel layer P_CH formed within a pipe gate layer PG, and a pair of source side channel layer S_CH and drain side channel layer D_CH connected with the pipe channel layer P_CH.
Further, the semiconductor memory device includes source side word line layers S_WL stacked along the source side channel layer S_CH on the pipe gate layer PG, and drain side word line layers D_WL stacked along the drain side channel layer D_CH on the pipe gate layer PG. Here, a source selection line layer SSL is stacked on the source side word lines S_WL, and a drain selection line layer DSL is stacked on the drain side word line layers D_WL.
According to the aforementioned structure, memory cells MC are stacked along the U-shaped channel layer CH, and a drain selection transistor DST and a source selection transistor SST are provided at both ends of the U-shaped channel layer CH, respectively. Accordingly, strings are arranged in a U-shape.
Further, the semiconductor memory device includes bit line layers BL connected with the drain side channel layer D_CH, to be extended in the first direction I-I′, and a source line layer SL connected with the source side channel layer S_CH, to be extended in the second direction II-II′.